EDA Design environment

EDA Design environment

ICsense has the largest fab-independent design group in Europe with analog and digital teams. This ensures full control over the most critical boundary in mixed-signal design, resulting in a low project risk.

Unique design environment

ICsense has developed a unique design environment for high-quality analog and digital design in a structured way, resulting in a high reliability and high first-time-right success rate. Industry standard EDA tools are combined with proprietary control software that automates several time-consuming steps in the design process, such as transistor size calculation, design plan based circuit sizing, visual simulation result processing and automated report generation. It allows the designer to focus on the inventive part of the design and prevents errors through the built-in systematic design flow.

Industry standard EDA tools

  • State-of-the-art simulators for analog, digital and mixed-signal ICs (see above). ICsense has developed methodologies to have fast and accurate full chip-level mixed-signal simulation coverage with these simulators.
  • Cadence – Virtuoso for schematic entry and layout
  • Complete digital flow down to GDS under one single roof, consisting of industry-standard EDA tools for simulation, synthesis, logic equivalence checking, STA, formal verification, place-and-route and ATPG test pattern generation.
  • Our state-of-the-art digital design flow is enhanced with in-house tools for otherwise error-prone processes and overall improved productivity.
  • Mentor Calibre for physical Verification (DRC/LVS) and parasitic extraction (xRC) and Analog FastSpiceā„¢ (AFS)
  • Version control and traceability with Cliosoft for analog schematics and layout and GIT for all digital development.
  • Matlab (including custom toolboxes) and Simulink for concept definitions and system design
  • Matlab script-based interface to formalize and automate circuit sizing, test-bench and simulation control, simulation data post-processing and report generation


Key benefits:

  • Structured and formalized design approach using design plans
  • Traceability of design choices and trade-offs through version control and design plans
  • Design and layout integrity through version control
  • Quality of final design and layout by formal issue tracking
  • Reliability of results by semi-automated simulation coverage and reporting
  • Extensive digital simulation coverage and constraint randomized verification

Key Features:

  • Top-down, bottom-up design methodology
  • Automated characterization over corners, supply and temperature
  • Powerful simulation result and corner data processing
  • Technology-independent platform
  • Simulator-independent platform
  • Embeds design plans for most analog blocks e.g. amplifier topologies, low dropout regulators, oscillators, bandgap references, temperature sensors, …
  • Code, condition, functional and assertion coverage in digital simulation
  • Version control
  • Issue tracking


  • DC-DC converters (inductive and capacitive / buck, boost, buck-boost, flyback)
  • Delta-sigma analog-to-digital converters
  • SAR analog-to-digital converters
  • Pipelined analog-to-digital converters
  • Delta-Sigma fractional-N synthesizers
  • Digital-to-analog converters
  • Phase-locked loops (PLL)

Start your ASIC journey here

Contact us now