Rik, Layout Engineer

Rik, Layout Engineer

Rik layout engineer at ICsenseRik joined ICsense in 2009 as a layout engineer after an early spell as a technician working on industrial LCD repairs. Prior to that, Rik came to electronics design via technical college and a childhood interest in technology, machines and electronics. 

WHAT INSPIRED YOUR INTEREST IN IC DESIGN?

My childhood interest in technology sparked my curiosity for electronics. I never felt there was any other area that would absorb me like electronics could. I am fascinated with what can be achieved with micro-electronics.

WHAT IS YOUR CURRENT DESIGN FOCUS?

Unlike electronic circuit design, IC layout design is a skill not widely taught at University. Rather, it is a skill learned from hands-on experience and mentors. Layout is about how an electrical circuit is physically laid down on silicon. The geometric device patterns and interconnect choices can have an enormous impact on performance. This is my focus. Now, with over 7 years’ experience behind me, I am mentoring others.

Most recently, I have been working on a 40 nm process node to optimise the area for a key analog building block. It’s fantastic working with leading edge process technologies.

WHY DID YOU CHOOSE ICSENSE?

The diversity of ICsense’s business fascinates me and it’s really stimulating to be involved in a wide array of different designs, helping bring ideas to life. Working with some of the best mixed-signal designers is of course another big plus.

WHAT STANDS OUT ABOUT ICSENSE AS AN EMPLOYER?

Planning helps ICsense work like a well-oiled machine. What’s more, there’s a real buzz here which you can’t miss. It’s a really open work environment where all contributions are appreciated. There is an undeniable focus on results, but equally there’s a good balance between hard work and community spirit.

WHAT IS YOUR TYPICAL WORK DAY LIKE?

Currently I am coaching junior engineers. I also have a lot of project planning work.

Even at a project’s conceptual stage, layout design is involved in the bid development process, since IC cost is largely dominated by the silicon area required. Area optimisation equates to cost optimisation and is determined by architectural design choices made, simulation outcomes and the resulting trade-offs. During the layout step, a theoretical electronic design is turned into physical reality and I love being part of that process.