Low-noise X-ray imaging chipset

Low-noise X-ray imaging chipset

The chipset is developed for large-scale, portable X-ray applications for a-Si backplanes. It consists of a high-voltage row-driver ASIC that controls the TFT pixels and a low-noise, column readout ASIC that reads the charges from the pixels.

The chipset achieves state-of-the-art noise levels with much lower power consumption and cost. The chips are assembled on the glass panel using chip-on-glass flip-chip technology with ACF. The ASICs are currently used in commercial X-ray imagers.


  • Static mode: 1 fps/ 14-bit/ 2.8 noise counts
  • Dynamic mode: 5 fps/ 4.4 noise counts (binning)
  • ROIC: 16 x 14-bit ADCs at 200kS/s, high-speed LVDS
  • Rows: 3456 / Columns: 2880: 10Mpixel
  • Chip on glass X-ray panel (Flip-chip, RDL)
  • High ball count: 216 I/Os per ASIC
  • 0.18um BCD technology

Chip Layout

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