Read the full article on Design News: https://www.designnews.com/semiconductors-chips/the-semiconductor-supply-risk-your-component-spec-doesn-t-capture

As geopolitical uncertainty fuels semiconductor supply risk, it isn’t just policymakers who need to respond. The implications for design engineers choosing components for their projects are significant, and more immediate than most procurement checklists reflect.

Every component selection a design engineer makes today contains a decision that the datasheet doesn’t describe. A semiconductor spec sheet might tell you about voltage rails, operating temperature, interface compatibility, and package options. It won’t tell you about the foundry your chip vendor depends on, the geographic concentration of its test and packaging capacity, or what happens to your supply programme if access to that foundry is disrupted.

Until recently, that gap didn’t matter much. It does now.

The semiconductor supply chain that engineering teams built their BOMs around for the last three decades was optimized for cost, availability, and performance under a stable set of geopolitical assumptions: reliable access to TSMC and Samsung capacity, predictable lead times, and foundry geography as a logistical rather than strategic variable.

Those assumptions were reasonable for most of that period. They have since been markedly repriced. The allocation disruptions of 2020 to 2022 accelerated awareness, but the shift is now structural. Both the US CHIPS Act and the EU Chips Act committed tens of billions of dollars to reshoring manufacturing capacity explicitly because policymakers reached the same conclusion: concentrated foundry geography is a supply chain vulnerability.

What that legislative conversation tends to miss, however, is that the risk exposure is not primarily a policy problem to be solved over a decade of fab construction. It’s about engineering decisions being made now, at the level of part selection.

What ‘fabless’ means for your supply chain exposure

The majority of chips designed into products over the last decade came from fabless companies – vendors who hold the design IP and the customer relationship but outsource manufacturing entirely to third-party foundries. This model generated remarkable engineering productivity, and the chips it produced are genuinely excellent. The point is not that fabless chips are a bad choice. The point is that selecting a fabless chip means inheriting that vendor’s foundry concentration as a supply risk.

A vendor whose entire production volume runs through a single foundry in a single geography carries a meaningfully different risk profile today than it did five years ago. That risk doesn’t appear anywhere on the datasheet. It doesn’t appear in most supplier qualification questionnaires. But for engineers working in markets where supply continuity is a safety or regulatory requirement – automotive, medical, industrial, defence-adjacent – it has become a legitimate dealbreaker.

What genuine fab-independence provides

The alternative to fab concentration is not vertical integration. Building semiconductor manufacturing is a multi-decade, multi-billion-dollar commitment, and even the new capacity being funded by the CHIPS Acts won’t come online at volume for years. The more immediately relevant alternative is to work with chip vendors that have genuine fab-independence: companies that can qualify and route production across multiple foundries, hold the engineering and customer relationship independent of which foundry does the manufacturing, and maintain in-house test capability that doesn’t move with the wafer.

This distinction matters. When a truly fab-independent design house encounters disruption at a primary foundry, the design IP, the test vectors, and the customer relationship don’t move with the problem. Production can be re-routed to a qualified alternative without restarting characterization and qualification from scratch. A locked-in fabless house – one whose design is qualified only on a single foundry’s process – has no equivalent contingency. Its supply resilience is, functionally, the same as the foundry’s.

Questions worth asking before you commit to a supplier

For engineers in high-volume commodity markets, standard parts from major catalogue suppliers will likely remain the right call for most applications, and the diversity of large foundry customers will provide a certain degree of structural resilience. But for engineers designing in regulated, long-lifecycle, or safety-critical environments, a different set of questions becomes relevant:

• Does your vendor maintain qualified production relationships across multiple foundries? Not just a claim of multi-foundry capability, but evidence of an actual transition between foundries for a shipping product (i.e. that required real engineering work, not just a second-source listing).
• Is wafer test capability held in-house, or outsourced to a single OSAT? Test is a chokepoint that rarely surfaces in supplier qualification conversations but can be as critical as foundry access when a disruption occurs.
• Does the engineering relationship reside at the design and IP level, or is it purely a commercial arrangement? Typically, it’s the former which is more likely to survive supply disruptions.

The custom ASIC case has a new argument

The custom ASIC route has always been evaluated against standard parts primarily on cost and schedule: higher NRE, longer development timeline, offset by optimized functionality and BOM simplification at volume. That trade-off is unchanged. What has changed is that a fab-independent custom ASIC partner – one that holds the design IP, qualifies across multiple foundries, and maintains in-house test capability – now brings a supply resilience argument that simply wasn’t part of the conversation five years ago.

ICsense designs custom ASICs for automotive, medical and industrial applications; markets where supply continuity is a regulatory and safety requirement rather than a preference. We maintain more than ninety design engineers, an in-house electrical wafer sort capability, and active foundry relationships across the globe. That philosophy – qualifying production across multiple foundries from the outset – has only become more relevant as geopolitical uncertainty has grown.

The broader policy debate about semiconductor sovereignty will run for many more years to come. New fab capacity being built now will come online over a decade-long timescale. None of that changes what engineers are deciding today, in this design cycle, about which chips go into which products. The repricing of foundry concentration risk has already happened. The question is whether the frameworks used to evaluate component suppliers have caught up with it.