This ASIC can measure the response of the brain after a neural stimulation. Since the neural stimulation requires signals in a higher voltage range, this architecture has an artefact reduction on-chip to cancel out the primary pulse. Focus of the design is on ultra-low-power and high-accuracy neural recording. The design is compliant to ISO13485.
- Application: Spinal cord stimulation, deep brain stimulation, …
- Neural recording during stimulation with artefact cancellation
- Ultra-low-power AFE of <40uA per channel
- Wide input range, low-noise (uVRMS) recording channels
- LNA with uVRMS noise-level and uA current consumption
- 15-bit low-power ADC (dual-cyclic pipelined architecture)
- Simultaneous signal processing of multiple recording channels:
- Digital artefact cancellation (based on LMS filter)
- Programmable band pass filters (incl. down-sampling)
- Hilbert Transformation incl. up-sampling, delay correction for signal correlation and dedicated CORDIC
- Oscilloscope mode (with parallel interface to stream data)
- Digital test features: JTAG, boundary scan, MBIST for memories
- 0.18u technology
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