The job location can be Leuven or Ghent.
Scope
A junior mixed-signal verification engineer performs mixed-signal verification and modeling of ASICs developed by ICsense.
Responsibilities
- Develop real-number behavioral models for analog/mixed-signal building blocks, perform modeling across projects (wreal and System Verilog real-number modeling). These models are used for mixed-signal verification
- Assist in setting up and executing mixed-signal verification across projects
- Contribute to improvements in real-number modeling and mixed-signal verification flow together with the senior mixed-signal verification engineers
- Assist design engineers in real-number modeling tasks
- Perform evaluations of new tools/methods that can improve the methodology
- Interact with the CAD team to improve the flow
- Communicate efficiently with the project team to successfully complete the project
Competences
- You have a master degree in Electrical Engineering
- You are interested to learn behavioral modeling of analog blocks and become experienced in System Verilog Real-Number Modeling and mixed-signal simulators like Cadence Xcelium
- You have a good knowledge of Matlab and programming skills are an asset (e.g. Python)
- You have strong communication and reporting skills, also in English
Our offer
- The job location can be Leuven or Ghent
- An attractive salary package with a variety of extra benefits
- A stimulating and pleasant working environment with regular team activities
- A financially healthy company with growth potential
- Possibility to continuously learn and grow through in-house and external trainings
