As part of ICsense’s full ASIC supply offering, we develop in-house ATE production tests to ensure high-quality, low-risk delivery of custom ICs. Our test engineers work closely together with our ASIC designers to align bench and production testing from the earliest design stages. Using Advantest V93K testers, ESMO handlers, and Accretech wafer probers, we create modular test flows that enhance quality and minimize risks. For low-to-medium volumes, production testing is handled in-house or with trusted OSAT partners. For high-volume manufacturing, ICsense collaborates with its parent company TDK or with its partner IDMs, leveraging their extensive mass production experience. This integrated approach ensures smooth industrialization, fast ramp-up, and reliable performance across all volumes.
Electrical Wafer Sort (EWS) is a key step in ICsense’s ASIC supply flow, used to electrically test each die on a wafer before packaging. It ensures only known-good-dies (KGDs) proceed to assembly and final test (if applicable), reducing cost and improving overall product yield. EWS is performed on Advantest V93K ATE platforms with Accretech wafer probers (8”/12”), supporting multi-site testing for high throughput.
Tests are conducted across temperature ranges to validate performance under real-world conditions. To screen for defects and statistical outliers, ICsense applies advanced techniques such as Part Average Testing (PAT) and Dynamic Voltage Stress (DVS) testing. Our in-house team develops custom hardware and ATE tests based on modular test flows to ensure maximum test coverage—crucial for quality and reliability —with minimum test time and cost.
(image courtesy: Technoprobe)
Final Test (FT) is the last step in ICsense’s ASIC supply flow, ensuring each packaged IC meets all functional and parametric specifications before shipment. It verifies performance under real-world conditions, including temperature testing, and screens for any defects missed during wafer sort. ICsense performs FT using Advantest V93K ATE systems and ESMO handlers, supporting multi-site testing for high throughput and cost efficiency.
Our in-house team develops custom load boards and uses a modular test flow to optimize test coverage and minimize test time. FT also enables post-packaging trimming and calibration, where parameters can be adjusted or programmed in the packaged unit, enabling the correction of minor manufacturing variations and the optimization of performance.
ICsense’s bench test lab plays a vital role in validating ASIC performance before production. The lab spans over 350 m² and is equipped for detailed functional testing, electrical characterization, and corner analysis across process, voltage and temperature ranges. Bench testing allows early verification of key parameters and supports debugging and optimization during development.
To ensure consistency between lab results and production testing, ICsense performs ATE correlation—aligning bench measurements with Automated Test Equipment (ATE) outcomes. This process guarantees accurate test coverage and reliable performance in mass production. The close interaction between design, bench, and test teams ensures smooth industrialization.
For low-to-medium volumes, ICsense offers in-house production testing or works with one of its OSAT (Outsourced Semiconductor and Test) partners.
For high-volume ASIC production, ICsense partners with its parent company TDK or with IDMs to ensure smooth industrialization and reliable mass manufacturing. TDK’s deep expertise in semiconductor operations and robust global infrastructure make them an ideal partner for scaling up production. ICsense manages the full ASIC development and test flow in-house, including ATE test program and hardware development. These are transferred to TDK—a process successfully proven already in multiple ASIC collaborations. By combining ICsense’s custom IC design and test expertise with the high-volume manufacturing capabilities of TDK or its partner IDM, customers benefit from a scalable, low-risk path to market for high-volume ASICs at a competitive price point.
