ICsense

ICsense offers a broad range of ASIC development services. These range from pure ASIC design to building full turnkey ASIC solutions including study, design, packaging, bench test, (ATE) production test, characterization, qualification and supply.
ICsense can manage the complete development chain from idea to final ASIC product. It can take responsibility for the ASIC supply chain through its network of preferred partners.
ICsense will custom-develop your ASIC according to your specific requirements. With the goal to implement optimal power consumption and/or performance at optimal cost.

This is how we can help in the 4 phases of a typical ASIC development:

Phase 1: Freeze the ASIC specification

In this phase, in close cooperation with you, the ASIC specification is frozen.
First, our ASIC design team performs an in-depth feasibility and architectural study, resulting in a list of potential trade-offs. In close interaction, and using this list, we will work on an optimal system architecture/concept with minimum area/cost and maximum functionality/performance.
The final outcome of this study will be an ASIC/system level architecture, including the building blocks specifications. We prove the feasibility through system level modelling/simulations and design equations.
Next, the foundry and technology node are selected. With this selection, the area, production and qualification costs will be assessed. From this, we can estimate the ASIC unit cost, which depends on your target volumes, the preferred package and the estimated production test time. Also the NRE pricing and timing for the development program will be fixed at the end of this phase.

Phase 2: Develop the prototype and production tests

In this phase we carry out the mixed-signal design and layout of the ASIC. We do elaborated simulations over process, voltage and temperature (PVT) variations and mismatch to make sure the design complies with the ASIC specification in all boundary conditions. We also do parasitic extraction to take potential layout parasitics into account during the simulations.  
Next, we fabricate ASIC prototypes and do both bench and statistical tests of the prototype ASICs. Prototyping of the ASIC will be done using a multi-layer mask set (MLM) or multi-project wafer run (MPW) to produce enough samples for statistical analyses. Both these prototyping options have a lower NRE cost compared to a single-layer mask set (SLM) production run.
While the ASIC prototypes are processed, we coordinate the development of the ATE (automated test equipment) tools. This custom-developed ATE hard- and software will be used during characterization and mass production, to verify every chip that is produced. This ensures that you only get chips compliant with the ASIC production test (ATE) specification. As part of this ATE procedure, the chips can also be calibrated and custom programmed according to your needs.
From the start of the design, we strongly emphasize Design for Testability (DFT) of the ASIC. This is needed so we can fully test the chip during bench/characterization tests and during mass production, and this in a cost-effective way. To that end, bench test hardware and software are custom-designed for your ASIC. When the prototypes return from the fab, we do bench testing of the ASICs over temperatures and supply voltages in our own labs. Full characterization (i.e. statistical tests) of the ASICs over temperatures and supply voltages is done on the ATE tools, to ensure a high yield and low ASIC cost. Finally, the ASIC undergoes ESD (electrostatic discharge) and latch-up tests to ensure a high reliability of the ASIC in the field.

Phase 3: Optimize the yield

In this phase, we optimize the ASIC prototype to reach the highest yield and to minimise the ASIC unit price. We do this based on the results of the phase 2 (characterization) tests.
We revise and optimize the ATE program to reduce the (mass) production test time and the ASIC unit price as much as possible. At the same time, we want to make sure that we only supply you with known good dies that are compliant with the ASIC production test (ATE) specification. Minimizing the mass production test time is essential, since this time seriously contributes to the ASIC production unit price. Last, optimized ASIC prototypes are fabricated and all phase 2 tests are repeated to ensure full compliance with the specification.

Phase 4: Qualification and production

First in this phase, a single layer mask set is generated as a basis to start the mass production. The ASIC is qualified by means of an industrialisation lot (of a few batches) and a skew lot.
From the devices in the industrialisation lot, statistical data will be collected and the production test limits of the (ATE) mass production test will be frozen.
The skew lot will be processed to prove the robustness of the ASIC over process variations (and potential process drifts) and to provide guarantees for the final yield/price. Statistical testing will be carried out on the different wafers of the skew lot. During production, each of the ASICs will be tested on the ATE to be compliant with the ASIC production-test specification.
Optionally, extra reliability tests can be carried out depending on the specific environmental operating conditions of the ASIC (i.e. mission profile) and/or specific customer requests to assure long-term ASIC compliance in operation. In most cases however qualification can be guaranteed by similarity.