Low-dropout (LDO) voltage regulator in 65nm CMOS
ICsense designed a state-of-the-art LDO regulator. Using our architectural toolboxes, we optimized the LDO regulator for efficiency, area and ripple specifications. In extreme conditions, the dropout can be as low as 0.15V. The regulator has a noise figure of < 50nV/√Hz at1MHz and consumes only 150uA in a typical condition. The LDO is designed in a 65nm CMOS process.
Features:
- Vin = 1.65 – 1.95V
- Vout = 1.25V to 1.5V (programmable)
- Offset is 1.8mV (1σ)
- Output load range is 0 – 27mA
- Silicon area is 0.046mm2
- Current consumption is below 200uA (typically 150uA)
- < 5µs settling (1%)
- 65nm CMOS technology
- Temperature range of -40°C to 100°C