A consumer accelerometer sensor interface ASIC in 0.18u CMOS
For one of its customers, ICsense did a design study for a 3-axis accelerometer readout ASIC for the consumer market (e.g. Wii-consoles, smartphones, GPS, …). This study resulted in a state-of-the-art architectural topology. It included the analog blocks modeled in Verilog A and system level specifications, architectures and block level simulations. The proposed process is 0.18u CMOS.
Features:
- Base capacitance of 400fF with 10 fF/g dynamic variation (+/- 2g to 16g selectable)
- Parasitic capacitance of 1.2pF compensated on-chip
- The Brownian noise is 128ug/sqrt(Hz)
- Over the consumer temperature range, the temperature error is below 1%
- The bandwith of the capacitive readout is 1kHz
- Current comsumption below 100uA
- The proposed process is 0.18u CMOS