High Voltage (10V) in a low voltage (1.8V), low cost process
ICsense’s high-voltage experts have invented a technique to implement high-voltage capabilities in standard, low-voltage technologies without the cost of extra process steps (read more on the publication at ISSCC in 2012). They successfully demonstrated this HVLC (high voltage low cost) technique in several designs:
- A capacitive DC-DC (200mW/mm2) with 10V output in plain 0.18u CMOS
- An inductive DC-DC for high power applications (1W/mm2)
- A class D audio output stage.
The HVLC technique is applied in a 1.8V/3.3V capable general-purpose digital I/O pad using only the 1.8V transistors in a 40nm GP TSMC technology. This I/O cell is available as IP-block.
Features:
- Enabling more than 4 times the VDD (e.g. 10V in a standard 0.18µm)
- Device terminal voltages always in SOA (safe operating area)
- Uses only low-voltage devices
- Based on more than 5 years of research
- One single low-voltage supply (VDD)
- Silicon qualified IP block: 3.3V digital IO in TSMC 40nm G 0.9V/1.8V
- Enabling technology for:
- Low-cost drivers/class D in plain CMOS
- Low-cost MEMS interfacing