Low power (1.8mA), low jitter (2.8 ps rms) fully integrated clean-up PLL
To provide synchronized and clean clock signals to high-accuracy sensing systems, ICsense has developed a state-of-the-art low-power clean-up PLL. The PLL synchronizes to and cleans up an incoming clock signal to provide a low power and stable clock signal. The PLL is fully integrated on an area of only 0.65mm2 and includes a ring oscillator, phase-frequency detection, a third order loop filter and a frequency divider. The ring oscillator is an advanced, differential and highly programmable architecture with measures to reduce white and 1/f related jitter. The power-jitter trade-off has been optimized to be close to the fundamental limits.
Features:
- Full integration of 8MHz PLL
- Low power consumption of 1.8mA
- Low jitter: 2.8 ps rms
- Phase noise: -135dBc/Hz at 400kHz
- Spurious emission: < -90dBc
- 0.18um CMOS technology
- -40°C to 100°C junction temperature